Clock signals are typically routed to various clocked circuit elements within a large circuit through a clock distribution network. In general, large drivers or buffers capable of providing large currents are used by the network to transmit the clock signals to the clocked circuit elements. Because large currents are used, the clock signals can couple to signal lines running parallel to the clock line. As a result, the clock signal can inject spurious signals or other noise into these signal lines.
In many conventional clock distribution networks, the clock lines are shielded to reduce the aforementioned coupling. Shielding is typically accomplished by routing ground lines parallel to the clock lines. In addition, in a multi-layer interconnect structure, ground lines parallel to the clock line are routed in the layers above and/or below the layer containing the clock line. For example, FIG. 1 shows a cross-sectional view of a portion of an interconnect structure 100 implemented in an integrated circuit with three metal layers. The interconnect structure 100 includes a clock line 101 in the top metal layer (i.e., the M3 layer). The interconnect structure 100 also includes a shield line 103 in the next lower metal layer (i.e., the M2 layer) that is parallel to and below the clock line 101 in the top metal layer. The shield line 103 is connected to a source of ground potential (not shown) and serves to shield a signal line 105 in the next lower metal layer (i.e., the M1 layer) having a portion running substantially parallel to and below the clock line 101. The ground line 103 helps prevent the coupling of clock signals propagated on the clock line 101 into the signal line 105 and any other signal lines in the M1 layer having a portion running parallel to the clock line 101.
FIG. 2 is a top view of the M3 layer of the portion of the interconnect structure 100 shown in FIG. 1. As shown in FIG. 2, the interconnect structure 100 also includes ground lines 201 and 203 running parallel to the clock line 101. The ground lines 201 and 203 serve to shield the clock line 101, thereby helping prevent coupling of clock signals propagated on the clock line 101 into other signal lines (not shown) located in the same layer (i.e., the M3 layer). In this embodiment, the ground line 103 located beneath the clock line 101 in the M2 layer is slightly greater in width than the clock line 101 and is shown in part with dashed lines.
Referring to FIGS. 1 and 2, because the ground line 103 is substantially continuous and located beneath the clock line 101, other signal lines in the same metal layer as the ground line 103 (i.e., the M2 layer) cannot be routed to cross beneath the clock line 101. As a result, any signal lines that need to cross the clock line 101 must be routed in another metal layer. For example, "crossing" signal lines can be routed in the next lower metal layer, i.e., the layer that contains the signal line 105. Consequently, the clock line 101, in effect, occupies two metal layers, thereby inefficiently utilizing the area available for routing signal lines in the interconnect structure 100. This inefficient routing may undesirably cause the interconnect structure 100 to include an additional metal layer, which increases the complexity and cost of the interconnect structure. Alternatively, the number of signal lines can be reduced, which can undesirably decrease the functionality of the circuitry coupled to the interconnect structure.